Paulami Das

Paulami Das

An AI/ML enthusiast experienced in the Semiconductor and healthcare field. Eager to build products and provide 360° support to ML solutions

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certifications

SQL Permalink

Published in https://www.hackerrank.com/certificates/9bd20b9ec536

The Data Scientist’s Toolbox Permalink

Published in https://www.coursera.org/account/accomplishments/verify/5FL7NBZM44VQ?utm_campaign=sharing_cta&utm_content=cert_image&utm_medium=certificate&utm_product=course&utm_source=link

PowerBI Essentials Permalink

Published in https://www.linkedin.com/learning/certificates/a7c1c1aa05b962b543afd29f402825ca929b83d1df6f065d278998dcc148b706?trk=backfilled_certificate

publications

A scalable solution to AlphaZero based Redundancy Analysis for semiconductor chips

Published in ICMLA 2022

Abstract – Manufacturing flaws in memory devices give rise to defective memory cells rendering the chips unusable and consequently reducing the wafer yield. To overcome the effect of faulty memory cells, redundancies are included in the form of spare rows and columns in the memory device. Redundancy Analysis (RA) is the process of mapping these spare rows and columns to repair faulty lines in the chip. Our previous work AlphaRA, an AlphaZero based Redundancy Analysis method, has demonstrated promising yields. However, training for large values of chip sizes (n) is time-consuming. In this paper, we introduce SAZRA, a scalable solution for AlphaZero based Redundancy Analysis algorithms with the use of Graph Neural Networks (GNNs). The memory chip is designed as a graph so that it can be used in GNNs, thus making the solution independent of n. With just a single training on a dataset of n=16 chips, we are able to achieve yields outperforming existing algorithms on n up to 128 times larger and previously unseen to the neural network. SAZRA maintains a high yield while having the least spare utilization across all chip sizes. It achieves scalability with reduction in training time, execution time, and GPU memory and disk memory requirements.

METHODS AND ELECTRONIC DEVICE FOR REPAIRING MEMORY ELEMENT IN MEMORY DEVICE

Published in US A1 Patent

Abstract – A method for repairing a memory device with faulty memory cells. The method includes defining a RA environment comprising a location of each of the faulty memory cells and a plurality of SR and a plurality of SC. The method further includes repairing the faulty memory cells based on an RA training process using the defined RA environment and mapping of the location of each faulty memory cell with the plurality of SC or SR. The method further includes training, based on a determination that indicates the at least one faulty memory cell among the faulty memory cells is left unrepaired and the at least one SC or SR is remaining, a first NN to perform an action for repairing of the faulty memory cells such that a maximum number of faulty memory cells are reparable and a minimum number of SC and SR are utilized during the repairing.